Two types of memory cell, the resistive load cell or the stacked 4T-2R cell, and the CMOS (complementary metal oxide semiconductor) cell or stacked 6T (transistor) cell, have been widely used in the VLSI SRAMs. Schematics of a stacked 6 T cell and a stacked 4T-2R cell are shown in FIGS. 1 and 2 respectively. Both the stacked 6T cell and the stacked 4T-2R cell of FIGS. 1 and 2 comprise two pass transistors 30 and two driver transistors 31.
Specific characteristics of these driver and pass transistors in addition to layout dimensions, such as those seen in FIG. 3, can in part determine the performance of the SRAM cell. For example, the .beta. ratio of a memory cell, which is one of the factors determining the stability of the cell, is a function of the width and length of the driver and pass transistor gates as shown below: ##EQU1## A high .beta. ratio reduces the soft error rate thereby improving the stability of the SRAM cell. The soft error rate is a measure of how easily the data stored in the cell can be altered in the presence of ionizing radiation. In other words, the soft errors refer to an upset or change of state of the cell typically due to ionizing alpha particles.
The length of the driver gate 22,24 shown in FIG. 3 is determined by length L.sub.D and the patterned driver gate electrode and is usually a minimum for a given technology. The width of the pass transistor Wp is determined by the width of the patterned moat region and is also usually a minimum for a given technology. To maximize .beta., it is then desired to maximize either W.sub.D or Lp. However, Lp is constrained since the pass transistor must provide for adequate current carrying capability. Thus, a large value of driver moat width W.sub.D is desired.
In FIG. 4, a large value driver moat width W.sub.D can be achieved for a given cell size for which no intra-cell moat-to-moat limitation is apparent. This is unlike prior art in FIG. 3 for which the width of the driver moat W.sub.D must be reduced to simultaneously maintain adequate moat-to-moat spacing 19.
In the fabrication of high density SRAMS, for example the one shown in FIG. 3, there are always concerns regarding intra-cell moat-to-moat spacing 19 due to isolation requirements. Moat-to-moat spacing 19 may be critical to maintain leakage currents at a minimum and to reduce overall the amount of moat-to-moat interaction. Therefore, the driver moat width W.sub.D is limited to meet the spacing requirements, having an adverse effect on the .beta. ratio. As cell area is reduced to, for example, 20 .mu.m.sup.2, the moat-to-moat spacing 19 is typically reduced to .ltoreq.0.6 .mu.m for conventional SRAM designs.